The present invention is related to a method and apparatus for adaptively predicting quantities of data to be prefetched in response to bus master read requests.
Computer systems commonly have one or more storage devices, such as random access memory, and busses that can used to transfer data from such storage device, to other devices within the computer system in a memory read transfer. These busses are often designed to support memory read transfers of small quantities of data, and these transfers are sufficient to support commonly occurring random reads from storage locations within a storage device. In the case of many busses, such memory read transfers begin with a distinct address phase in which the address of the storage location from which data is to be retrieved is transmitted to the storage device. This is then followed by a distinct data phase in which a single transfer of data takes place. If more data is to be retrieved, then additional memory read transfers must be performed, each having both address and data phases. However, such memory read transfers are inefficient for use in retrieving a larger quantity of data from a group of adjacent storage locations within a storage device.
Various higher performance busses support a form of transfer commonly referred to as a xe2x80x9cburstxe2x80x9d transfer in which there is one address phase, followed by multiple data Phases. In this way, efficiency can be increased for memory transfers from a larger number of adjacent storage locations by transmitting only the address of the first storage location. The first data phase entails the transfer of data from the storage location within the storage device that was specified by the transmitted address, and the subsequent data phases entail the transfer of data from adjacent storage locations. This is commonly referred to as a xe2x80x9cburst read transfer.xe2x80x9d In some higher performance busses, burst read transfers can be interrupted or suspended between the address phase and the first data phase, or between data phases, in order to allow the bus to be made available for other uses.
A common drawback in the implementation of various busses supporting burst read transfers, however, is that the bus does not provide a way for a device requesting a burst read transfer, such as a bus master device, to specify the exact quantity of data desired. Some bus implementations allow a bus master device to begin a burst read transfer, and then simply continue to perform data phases in that burst read transfer until the bus master device has received the desired quantity of data. This means that the exact quantity of data to be transferred cannot be known until the transfer has been completed.
The fact that the quantity of data to be transferred in a burst read transfer cannot be known until the transfer has ended impairs efforts to optimize the reading of data for such transfers from a storage device. This can be especially true in the case of burst read transfers from such storage devices as random access memory (RAM). Some forms of RAM impose considerable latencies on accesses to storage locations to read data, resulting in adverse effects on the performance of burst read transfers. Were it possible to know the exact quantity of data to be read for a burst transfer, it might be possible to use various well known techniques to counteract the effects of such latencies, and the performance of such burst transfers could be improved.
An apparatus and method for predicting quantities of data required by requesting devices capable of requesting unspecified quantities of data from storage devices, in which patterns of quantities required in past transfers are monitored. Predictions are made based on those patterns, associated with a pattern, used to make requests for data from storage devices, and selectively modified if they prove to be inaccurate.